DocumentCode
2879113
Title
A self calibrating 12b 12 µ s CMOS ADC
Author
Hae-Sung Lee ; Hodges, D.A. ; Gray, P.
Author_Institution
Univ. of California, Berkeley, CA, USA
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
64
Lastpage
65
Abstract
Linearity errors of a weighted-capacitor ADC have been corrected, using a simple digital algorithm. A CMOS comparator which resolves 50μV in 500ns, allows this approach to yield a 12b accurate conversion in 22us. Chip area is under 7mm2.
Keywords
Analog-digital conversion; Calibration; Circuit testing; Delay; Latches; MOS capacitors; Resistors; Semiconductor device measurement; System testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156622
Filename
1156622
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