Title :
A sub nanosecond 8K-gate CMOS/SOS gate array
Author :
Tanaka, Shoji ; Jun Iwamura ; Ohno, Jun ; Maeguchi, K. ; Tango, H. ; Katsuyuki Doi
Author_Institution :
Toshiba Semicond. Device Engin. Lab., Kawasaki, Japan
Abstract :
A CMOS/SOS 8370-gate array has been developed using a 2μm Si-gate process. Typical propagation delay time for the 2-input NAND gate with a fan out of 3 and 2mm of metal interconnect loading is 0.87ns.
Keywords :
CMOS logic circuits; CMOS technology; Delay effects; Large scale integration; Logic arrays; Parasitic capacitance; Propagation delay; Semiconductor devices; Testing; Wire;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156671
