DocumentCode
2880179
Title
A VLSI delay commutator for FFT implementation
Author
Swartzlander, E. ; Young, William ; Joseph, Sadiku
Author_Institution
TRW Defense Systems Group, Redondo Beach, CA, USA
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
266
Lastpage
267
Abstract
The implementation of a 108,000 transistor delay/commutator circuit for realization of FFT processors achieving data rates of up to 40MHz, will be described. The circuit contains 12,288 shift register stages and about 2000 logic gates, and implemented with 2.5μm CMOS standard cell technology.
Keywords
Acoustic signal processing; Counting circuits; Delay; Digital signal processing chips; Radar signal processing; Shift registers; Signal processing algorithms; Speech processing; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156682
Filename
1156682
Link To Document