• DocumentCode
    2880195
  • Title

    A 288Kb CMOS pseudo SRAM

  • Author

    Kawamoto, Hiroaki ; Yamaguchi, Yoshio ; Shimizu, Shogo ; Ohishi, Kiyoshi ; Tanimura, N. ; Yasui, T.

  • Author_Institution
    Hitachi Device Dev. Center, Tokyo, Japan
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    276
  • Lastpage
    277
  • Abstract
    This paper will report on an externally nonclocked 32K×9b PSRAM that employs an N channel dynamic transistor cell, 6.8μm \\times 13.6\\mu m, with 5.58mm × 9.86mm die size.
  • Keywords
    CMOS memory circuits; Capacitance; Clocks; Costs; Delay lines; MOS devices; Power dissipation; Random access memory; Read-write memory; Signal generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156683
  • Filename
    1156683
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2880195