• DocumentCode
    2880827
  • Title

    A 20ns 64K NMOS RAM

  • Author

    Schuster, Stefan ; Chappell, B. ; DiLionardo, V. ; Britton, P.

  • Author_Institution
    IBM Res. Center, Yorktown Heights, NY, USA
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    226
  • Lastpage
    227
  • Abstract
    A 32.6mm24K×16 NMOS SRAM having a 20ns access time and 30ns cycle time will be covered. The SRAM utilizes a 4 transistor dynamic refresh memory cell with 1.7μm features and single level polycide.
  • Keywords
    Capacitance; Clocks; Decoding; Driver circuits; Fault location; MOS devices; Sampling methods; Switches; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156718
  • Filename
    1156718
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2880827