Title :
A 32 bits architecture for an AES system
Author :
Pongyupinpanich, S. ; Phathumvanh, S. ; Choomchuay, S.
Author_Institution :
Dept. of Electron., King Mongkut´´s Inst. of Technol., Bangkok, Thailand
Abstract :
This paper describes a compact 32 bit architecture developed for the Rijndael cyphering/decyphering system. The implementation complies with the NIST Advanced Encryption standard. The design processes 128-bit block data with 128-bit key. For an area-saving implementation, the field inversion block and the key scheduling circuits are shared by both the encryption and decryption process.
Keywords :
Galois fields; code standards; cryptography; field programmable gate arrays; AES system; Galois fields; NIST Advanced Encryption standard; Rijndael cyphering/decyphering system; compact 32 bit architecture; decryption; encryption; field inversion block; field programmable gate arrays; key scheduling circuits; Application software; Computer architecture; Cryptography; Electronic mail; Field programmable gate arrays; Hardware; Information technology; NIST; Process design; Scheduling;
Conference_Titel :
Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on
Print_ISBN :
0-7803-8593-4
DOI :
10.1109/ISCIT.2004.1412452
