Title :
A 1ns 20K CMOS gate array series with configurable 15ns 12K memory
Author :
Takayama, Yoichiro ; Fujii, Shohei ; Tanabe, Takasumi ; Kawauchi, Kiyoto ; Yoshida, Takafumi ; Yamashita, Katsumi
Author_Institution :
Fujitsu, Ltd., Kawasaki, Japan
Abstract :
A CMOS array providing a maximum of 20,000 logic gates or logic and memory will be described. Typical gate delays of 1.0ns and memory access time of 15ns have been obtained using a 1.5μ twin tub process.
Keywords :
CMOS technology; Circuit testing; Clocks; Logic arrays; Logic circuits; Logic testing; Pins; Random access memory; Read-write memory; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156742
