Applying high-level synthesis techniques to FPGA-based design

This paper describes a prototype of an automatic behavioural synthesis system targetted at FPGA-based reconfigurable digital systems. Experiments with the system, especially for synthesising random number generators, shows that register-transfer level hardware costs do not reflect hardware costs in terms of FPGA resource (e.g. Xilinx CLBs). This shows that extensive efforts that have been spent in the past for optimizing RTL-hardware costs need to be reconsidered. For this particular example, a simple register allocation (i.e. no register allocation at all) is much better than register allocation based on the left-edge algorithm. Experiments in synthesising random number generators involving both FPGAs and RAMs also shows that behavioural equivalent circuits with the same number and types of RTL-hardware units require different number of CLBs