DocumentCode
2881990
Title
A 2K × 9 dual port memory
Author
Barber, F. ; Eisenberg, D. ; Ingram, G. ; Strauss, Michael ; Wik, Torsten
Author_Institution
AT&T Bell Laboratories, Allentown, PA, USA
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
44
Lastpage
45
Abstract
A 2K×9 CMOS dual port RAM linking asynchronous data between processor systems will be reported. Memory provides separate access ports and internally resolves conflicting access requests. Circuit combines a timed shared CMOS SRAM with logic to achieve a contention-induced error rate of less than 100 FITS.
Keywords
CMOS logic circuits; CMOS process; Decoding; Logic arrays; Multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156787
Filename
1156787
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