Title :
Power-Gating Schemes for Ultra-Thin SOI (UTSOI) Circuits in Hybrid SOI-Epitaxial CMOS Structures
Author :
Lo, Shih-Hsien ; Das, Koushik K. ; Chuang, Ching-Te ; Sleight, Jeffrey W.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY
Abstract :
Several novel schemes of implementing MTCMOS circuits in hybrid UTSOI-epitaxial CMOS structures are proposed and analyzed through comprehensive circuit simulations. The schemes offer intrinsic high circuit density and facilitate header/footer body biasing techniques for performance enhancement and leakage reduction. The effectiveness in improving active-mode performance, and reducing virtual supply bounce and standby leakage power is demonstrated
Keywords :
CMOS integrated circuits; integrated circuit modelling; silicon-on-insulator; circuit density; circuit simulations; header/footer body biasing; hybrid SOI-epitaxial CMOS; leakage power; leakage reduction; multithreshold CMOS circuits; power-gating schemes; ultra-thin SOI circuits; virtual supply reduction; CMOS logic circuits; CMOS technology; Capacitance; Circuit analysis; Circuit simulation; Epitaxial layers; FETs; Logic circuits; Logic devices; MOS devices;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258120
