Module-level matching algorithms for MSM clos-network switches

In this paper, we propose a simple module-level matching scheme for memory-space-memory Clos-network switches to avoid complex path-allocation algorithms in bufferless Clos networks, as well as cell out-of-order and saturation-tree problems in buffered Clos networks. We show that the module-level matching scheme can achieve 100% throughput.We propose static and dynamic dispatching cell schemes in addition to the module-level matching to improve the delay performance. The static cell dispatching scheme requires no additional scheduling; while the dynamic cell dispatching scheme is more adaptive to the traffic than the static one, thus can achieve better delay performance under non-uniform traffic loads. However, the wiring complexity of the scheduler for dynamic cell dispatching is high. Thus, the grouped dynamic cell dispatching scheme is proposed as a trade-off between the complexity and performance. In practice, embedded memory size is restricted, thus the queue length limitation in each switch module is also considered in this paper. We propose an efficient scheme to prevent queues to overflow in this situation which makes our work more practical.