• DocumentCode
    2883200
  • Title

    A triple-level wired 24K gate CMOS gate array

  • Author

    Saigo, Tatsuya ; Niwa, Kenta ; Ohto, T. ; Kurosawa, Shunsuke ; Takada, Tatsuo

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    122
  • Lastpage
    123
  • Abstract
    This paper will describe an array using adjacent double transistor columns and 2μ design rules for a 12.8×12.8mm2chip. Implementation of a digital signal processor with 19.3K gates of RAM, multiply, ALU and control logic will be compared with a full custom design.
  • Keywords
    Digital signal processors; Joining processes; Large-scale systems; Logic arrays; Logic circuits; Process design; Routing; Signal design; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156854
  • Filename
    1156854
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2883200