DocumentCode
2883390
Title
A 8 × 8b parallel multiplier in submicron technology
Author
Lee, Jeyull ; Garvin, H. ; Slayman, C. ; Mento, R.
Author_Institution
Hughes Research Laboratories, Malibu, CA, USA
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
84
Lastpage
85
Abstract
This paper will describe a 16ns 8×8b amplifier fabricated with an 0.85μ gatelength NMOS process. The chip (0.61mm× 0.85mm) containes 1427 transistors, dissipates 600mW and has a 420ps average gate delay.
Keywords
MOS devices;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156866
Filename
1156866
Link To Document