DocumentCode :
2883433
Title :
Modeling and Testing of Intra-Cell Bridging Defects Using Butterfly Structure
Author :
Ko, Lu-Yen ; Huang, Shi-Yu ; Chiou, Jia-Liang ; Cheng, Han-Chia
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu
fYear :
2006
fDate :
26-28 April 2006
Firstpage :
1
Lastpage :
4
Abstract :
We address in this paper the defect modeling and testing of intra-cell bridging defects from the layout perspective. For defect modeling, we incorporate a butterfly structure to resolve the potential non-logical effect a bridging defect may cause. By doing so, a realistic Boolean fault model at the gate level can thus be generated for each defect under consideration. Furthermore, the test vectors can be generated by a formulation on top of existing ATPG tools. Experimental results indicate that simple stuck-at test set can only achieve 85% coverage for intra-cell bridging defects for ISCAS85. The proposed systematic flow can further boost it to 99%
Keywords :
Boolean functions; automatic test pattern generation; fault diagnosis; integrated circuit modelling; integrated circuit testing; logic testing; ATPG tools; Boolean fault model; automatic test pattern generation; butterfly structure; defect modeling; intra-cell bridging defects; nonlogical effect; stuck-at test set; Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Fault detection; Fault diagnosis; Integrated circuit interconnections; Logic testing; System testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
Type :
conf
DOI :
10.1109/VDAT.2006.258149
Filename :
4027521
Link To Document :
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