DocumentCode
2883559
Title
An All-Digital Duty Cycle Corrector
Author
Chen, Bo-Jiun ; Kao, Shao-Ku ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
fYear
2006
fDate
26-28 April 2006
Firstpage
1
Lastpage
4
Abstract
An all-digital 50% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50%. This digital DCC has been implemented in a 0.35mum 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 17.3ps at 600MHz. Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz
Keywords
CMOS digital integrated circuits; delay lines; jitter; 0.35 micron; 16 mW; 17.3 ps; 250 to 600 MHz; CMOS process; all-digital duty cycle corrector; half delay line; peak-peak jitter; wide input duty cycle range; Circuits; Clocks; Delay effects; Delay lines; Energy consumption; Frequency; Pulse generation; Quantization; Signal generators; Space vector pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0179-8
Electronic_ISBN
1-4244-0180-1
Type
conf
DOI
10.1109/VDAT.2006.258158
Filename
4027530
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