DocumentCode :
2883928
Title :
A 3ns 32K bipolar RAM
Author :
Yuen Chan ; Brown, Jason ; Nijhuis, R. ; Rivadeneira, C. ; Struk, J.
Author_Institution :
IBM General Technology Division, Hopewell Junction, NY, USA
Volume :
XXIX
fYear :
1986
fDate :
19-21 Feb. 1986
Firstpage :
210
Lastpage :
211
Abstract :
A 3ns 32K bipolar SRAM with an unclamped complementary transistor switch memory cell, affording the advantages of 20%-30% smaller area, higher soft error immunity and improved leakage tolerance, will be described. A polysilicon trench isolation process with 1.5μm lithography provided a die area of 33.5mm2.
Keywords :
Capacitance; Decoding; Driver circuits; Isolation technology; Lithography; Pulsed power supplies; Random access memory; Read-write memory; Switches; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1986.1156896
Filename :
1156896
Link To Document :
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