Title :
Performance evaluation of exclusive cache hierarchies
Author :
Zheng, Ying ; Davis, Brian T. ; Jordan, Matthew
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan Technol. Univ., Houghton, MI, USA
Abstract :
Memory hierarchy performance, specifically cache memory capacity, is a constraining factor in the performance of modern computers. This paper presents the results of two-level cache memory simulations and examines the impact of exclusive caching on system performance. Exclusive caching enables higher capacity with the same cache area by eliminating redundant copies. The experiments presented compare an exclusive cache hierarchy with an inclusive cache hierarchy utilizing similar L1 and L2 parameters. Experiments indicate that significant performance advantages can be gained for some benchmark through the use of an exclusive organization. The performance differences are illustrated using the L2 cache misses and execution time metrics. The most significant improvement shown is a 16% reduction in execution time, with an average reduction of 8% for the smallest cache configuration tested. With equal size victim buffer and victim cache for exclusive and inclusive cache hierarchies respectively, some benchmarks show increased execution time for exclusive caches because a victim cache can reduce conflict misses significantly while a victim buffer can introduce worst-case penalties. Considering the inconsistent performance improvement, the increased complexity of an exclusive cache hierarchy needs to be justified based upon the specifics of the application and system.
Keywords :
benchmark testing; cache storage; memory architecture; performance evaluation; benchmarks; cache configuration; cache memory capacity; exclusive cache hierarchy; execution time increase; execution time metrics; inclusive cache hierarchy; memory hierarchy performance; performance evaluation; performance improvement; system performance exclusive caching; two-level cache memory simulations; victim buffer; victim cache; Benchmark testing; Cache memory; Cache storage; Circuits; Computational modeling; Delay; Microprocessors; Modems; Random access memory; System performance;
Conference_Titel :
Performance Analysis of Systems and Software, 2004 IEEE International Symposium on - ISPASS
Print_ISBN :
0-7803-8385-0
DOI :
10.1109/ISPASS.2004.1291359