DocumentCode
2885131
Title
A bipolar 32b processor chip
Author
Buckley, F. ; Chen, S. ; Hilse, J. ; Homan, Mihai ; Machol, G. ; Pereira, Luis ; Terry, Jack ; Watanabe, G.
Author_Institution
IBM Corporation, Los Gatos, CA, USA
Volume
XXIX
fYear
1986
fDate
19-21 Feb. 1986
Firstpage
30
Lastpage
31
Abstract
The architecture, circuitry, packaging and design of a 14×16mm 32b CPU chip dissipating 16W will be described. The chip, which has been built in a 2μm bipolar process with 8-level cascode ECL circuitry, executes a mainframe instruction set.
Keywords
Automatic control; Breakdown voltage; Delay; Diodes; Insulation; Logic design; Pins; Registers; Switches; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location
Anaheim, CA, USA
Type
conf
DOI
10.1109/ISSCC.1986.1156966
Filename
1156966
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