A single-electron shut-off transistor for a scalable sub-0.1 /spl mu/m memory

Author

Osabe, T. ; Ishii, T. ; Mine, T. ; Murai, F. ; Yano, K.

Author_Institution

Hitachi Central Res. Lab., Tokyo, Japan

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

301

Lastpage

304

Abstract

The developed single-electron shut-off (SESO) transistor has a leakage current in the range of 10/sup -19/ A (less than one electron per 100 ms; typical DRAM refresh cycle) or better, and it ushers in an era of opportunities for 4-Gb-or-larger post-DRAM memories. In its ultra-thin (2 nm) polycrystalline silicon film, electron hopping between traps is dramatically suppressed because of its limited number of neighboring traps and the Coulomb blockade effect. A SESO memory gain cell using the SESO transistor, has an over 3,000 second retention time even without a memory capacitor.

Keywords

Coulomb blockade; cellular arrays; field effect memory circuits; hopping conduction; leakage currents; single electron transistors; 1E-19 A; 2 nm; 3000 sec; 4 Gbit; Coulomb blockade effect; DRAM refresh cycle; SESO memory gain cell; electron hopping; leakage current; polysilicon film; retention time; scalable sub-0.1 /spl mu/m memory; single-electron shut-off transistor; Capacitors; Electron traps; Leakage current; MOSFET circuits; Random access memory; Silicon; Single electron transistors; Switches; Thin film transistors; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904316

Filename

904316