Two architectures for implementing RBF neural networks

This paper describes two methods for implementing radial basis function (RBF) neural networks using CMOS. The first method (i.e., the parallel method) is designed to maximally exploit the parallelism of neural computing. The distance between an input vector and each of the stored prototypes is calculated at the same time in the parallel method. The concept of an input plane and an output plane is introduced in the parallel method. The second method (i.e., the serial method) is designed to minimize the chip area required to implement the RBF network. The distance between an input vector and each of the stored prototypes is calculated sequentially in the serial method. Two buses (i.e., the weight bus and the threshold-value bus) are introduced in the serial method. All circuits used in the serial and parallel methods are presented and simulated using SPICE. The entire network is verified by SPICE using two examples. Performance comparison of using the serial and parallel methods is also presented