Author :
Imai, K. ; Yamaguchi, K. ; Kudo, T. ; Kimizuka, N. ; Onishi, H. ; Ono, A. ; Nakahara, Y. ; Goto, Y. ; Noda, K. ; Masuoka, S. ; Ito, S. ; Matsui, K. ; Ando, K. ; Hasegawa, E. ; Ohashi, T. ; Oda, N. ; Yokoyama, K. ; Takewaki, T. ; Sone, S. ; Horiuchi, T.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan
Abstract :
This paper describes a 0.13-/spl mu/m-generation CMOS technology optimized for system-on-a-chip (SoC) applications. The wide-range of performances obtained using a triple gate oxide and multiple threshold voltage control allows the SoC to operate at high speed with low standby power. Core CMOS transistors, which have a 1.9 nm gate oxide and a 95-nm physical gate length, show an excellent drive current of 740/335 /spl mu/A//spl mu/m at 1.2 V. Low power CMOS transistors have a standby current of only 2-0.2 pA//spl mu/m with a 2.6-nm gate oxide and a 120-nm gate length. This technology has also been used to make a 1.4-/spl mu/m/sup 2/ loadless 4T SRAM cell as well as a 2.5-/spl mu/m/sup 2/ 6T cell. The wiring RC delay has been reduced by integrating Cu interconnects with a low-k "ladder-oxide" layer.
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit optimisation; delays; high-speed integrated circuits; integrated circuit reliability; leakage currents; low-power electronics; 0.13 micron; 1.2 V; 1.9 nm; 120 nm; 2.6 nm; 95 nm; CMOS device optimization; SRAM cell; drive current; gate length; gate oxide; ladder-oxide layer; multiple threshold voltage control; physical gate length; standby current; standby power; system-on-a-chip applications; triple gate oxide; wiring RC delay; CMOS technology; Delay; Implants; Indium tin oxide; Leakage current; National electric code; System-on-a-chip; Threshold voltage; Ultra large scale integration; Wiring;
