Title :
Impact of process scaling on 1/f noise in advanced CMOS technologies
Author :
Knitel, M.J. ; Woerlee, P.H. ; Scholten, A.J. ; Zegers-Van Duijnhoven, A.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Sv/sub gate/ has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Sv/sub gate/ can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.
Keywords :
1/f noise; CMOS integrated circuits; doping profiles; integrated circuit modelling; integrated circuit noise; Hung model; ITRS roadmap; advanced CMOS technologies; gate bias; gate-oxide thickness; input-referred spectral 1/f noise density; process scaling; substrate dope; CMOS process; CMOS technology; Charge measurement; Charge pumps; Current measurement; Density measurement; Frequency; Interface states; MOS devices; Thickness measurement;
Conference_Titel :
Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6438-4
DOI :
10.1109/IEDM.2000.904356
