An analog VLSI neural network architecture with on-chip learning

A user-configurable analog VLSI feedforward neural network architecture that adds only 10% to chip area relative to a fixed topology is described. Central to the architecture is a novel synapse circuit that consumes 4500 μm² in a 2-μm technology. Hybrid dynamic and non-volatile weight storage allows fast learning as well as reliable long-term storage. Measured synapse current-voltage curves from a test chip are presented. The synapse includes a weight increment circuit that adds offset of only 1 part in 13 bits allowing analog-domain on-chip learning. Weight update circuits that implement a semiparallel weight perturbation learning algorithm are presented