A BiMOS programmable divider

Author

Choy, C.S. ; Ho, C.Y. ; Lunn, Gerald ; Lin, Benny ; Fung, Gary ; Chiu, Raymond

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong

fYear

1991

fDate

16-17 Jun 1991

Firstpage

768

Abstract

The authors describe a BiMOS programmable divider which draws an optimum mix of ECL And CMOS to achieve operating frequency of 165 MHz. Combined with a divide-by-eight prescalar stage, frequencies up to 1.3 GHz can be handled. The programmable divider contains 15 stages of flip-flops configured as a ripple down counter. The first three low order bits are ECL stages and the rest are CMOS stages. Simulation results have suggested that the divider can achieve a division range of 8 to 32767 in steps of unity. Also the reduction of power consumption and the size of the programmable divider are only 35% of a bipolar counterpart

Keywords

BIMOS integrated circuits; flip-flops; frequency dividers; integrated logic circuits; 1.3 GHz; 16 MHz; BiCMOS IC; BiMOS; CMOS stages; ECL stages; decoding; divide-by-eight prescalar; flip-flops; programmable divider; reloading; ripple down counter; CMOS logic circuits; CMOS technology; Clocks; Counting circuits; Decoding; Energy consumption; Flip-flops; Frequency conversion; Latches; Logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on

Conference_Location

Shenzhen

Type

conf

DOI

10.1109/CICCAS.1991.184473

Filename

184473