DocumentCode :
2887508
Title :
A via minimization channel router for three-layer channel with irregular boundaries
Author :
Song, Xuejun ; Li, Wangchao ; Liu, Meilun
Author_Institution :
Dept. of Electr. Eng. & Autom., Tianjin Univ., China
fYear :
1991
fDate :
16-17 Jun 1991
Firstpage :
870
Abstract :
In LSI/VLSI chip layout design, channel routing is one of the key steps. Generally, boundaries of the channel are two parallel lines. But sometimes, because of the different sized cells or macro cells, there may be some indentations on boundaries of the channel. In this paper, a channel router for three-layer channel with irregular boundaries is presented. Both the number of vias and the number of tracks are taken as the objectives. This algorithm has been coded in Pascal and implemented. The experimental results are satisfactory
Keywords :
Pascal; VLSI; circuit layout CAD; large scale integration; LSI; Pascal; VLSI; indentations; irregular boundaries; macro cells; three-layer channel; tracks; via minimization channel router; Compaction; Design automation; Filling; Large scale integration; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on
Conference_Location :
Shenzhen
Type :
conf
DOI :
10.1109/CICCAS.1991.184500
Filename :
184500
Link To Document :
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