A via minimization channel router for three-layer channel with irregular boundaries

In LSI/VLSI chip layout design, channel routing is one of the key steps. Generally, boundaries of the channel are two parallel lines. But sometimes, because of the different sized cells or macro cells, there may be some indentations on boundaries of the channel. In this paper, a channel router for three-layer channel with irregular boundaries is presented. Both the number of vias and the number of tracks are taken as the objectives. This algorithm has been coded in Pascal and implemented. The experimental results are satisfactory