DocumentCode
2887955
Title
Balancing productivity and performance on the cell broadband engine
Author
Alam, Sadaf R. ; Meredith, Jeremy S. ; Vetter, Jeffrey S.
Author_Institution
Oak Ridge Nat. Lab., Oak Ridge, TN
fYear
2007
fDate
17-20 Sept. 2007
Firstpage
149
Lastpage
158
Abstract
The cell broadband engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instruction-multiple-data (SIMD) cores. Each core is capable of very high performance; however, users must explicitly manage data movement, scheduling, and synchronization. While these attributes provide some of the cell processorpsilas greatest performance strengths, they also form its greatest weaknesses in terms of developer productivity, code portability, and initial performance efficiencies. In this paper, we evaluate productivity and relative performance improvements of a cell BE system for a diverse set of kernels and applications. Our experimental workload includes algorithms from scientific, cognitive, and imaging problem domains. Our results demonstrate that the cell processor could be several times faster than a SSE-enabled, contemporary dual-core processor, and could sustain a high performance-to-productivity ratio. We outline strategies for transforming applications to exploit the cellpsilas architectural features, and measure productivity by comparing programming effort in terms of lines of code and performance. For instance, our measurements revealed that a covariance matrix creation routine - a common routine in hyperspectral imaging - ran over eight times faster than a 2.66 GHz Intel Woodcrest processor while sustaining a productivity metric of over two by parallelizing across the heterogeneous cores, unrolling loops, and improving instruction level parallelism with SIMD instructions in a high-level language.
Keywords
microprocessor chips; parallel processing; Intel Woodcrest processor; cell broadband engine; code portability; data movement; developer productivity; general-purpose POWER architecture core; heterogeneous multicore processor; hyperspectral imaging; independent single-instruction-multiple-data cores; performance-to-productivity ratio; Covariance matrix; Engines; High level languages; Hyperspectral imaging; Kernel; Multicore processing; Power system management; Processor scheduling; Productivity; Radio access networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Cluster Computing, 2007 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1552-5244
Print_ISBN
978-1-4244-1387-4
Electronic_ISBN
1552-5244
Type
conf
DOI
10.1109/CLUSTR.2007.4629227
Filename
4629227
Link To Document