Parallel computing system with communication memory

The authors describe a parallel computing system architecture in which the processors´ access to common data is combined with the memory read/write operations. This can be achieved by the division of the memory into individual modules constituting the communication memory. Only data which are used by at least two processors of the parallel computing system are written into the memory. The communication memory organization has been studied with a view to accessed data movement during the computations. Each processor is capable of reading and writing in the memory of the other processors