Title :
Research on LL-DPLL changing order automatically
Author :
Fuqiang, Yao ; Juesheng, Zhang ; Wulin, Du
Author_Institution :
Dept. of Inf. Eng., Xi Dian Univ., Xian, China
Abstract :
In order to solve the contradiction between rapid bit-synchronization and filtering the phase noise, a new lead-lag digital phase locked loop (LL-DPLL) is proposed, the design considered and the principle of operation presented in this paper. The theoretical analyses and the experimental results are given also
Keywords :
digital circuits; phase-locked loops; synchronisation; DPLL; bit-synchronization; digital phase locked loop; filtering; lead-lag digital PLL; phase noise; Circuits; Difference equations; Filtering; Filters; Frequency conversion; Phase detection; Phase noise; Pollution; Switches; Tires;
Conference_Titel :
Circuits and Systems, 1991. Conference Proceedings, China., 1991 International Conference on
Conference_Location :
Shenzhen
DOI :
10.1109/CICCAS.1991.184531
