Analysis of power-performance for Ultra-Thin-Body GeOI logic circuits

This work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI devices/circuits, the band-to-band tunneling dominated leakage currents of GeOI devices/circuits show less sensitivity to temperature. At 300°K and comparable delay, GeOI inverter with smaller band-gap shows larger leakage than the SOI inverter at Vdd = 1.0V, while exhibits lower leakage than the SOI inverter at Vdd = 0.8V. At 400°K, GeOI inverter shows both lower leakage and lower delay at Vdd = 0.6~1.0V compared with the SOI counterpart, due to the weaker temperature dependence of band-to-band tunneling leakage compared with subthreshold leakage. Compared with the SOI Two-Way NAND and NOR, the GeOI Two-Way NAND and NOR show smaller leakage currents at Vdd = 0.5V or 400°K as the band-to-band tunneling leakage is less sensitive to temperature compared with the subthreshold leakage. Compared with the GeOI domino gate at 400°K, the SOI domino gate shows 5 times degradation in the worst-case noise (dynamic node voltage droop) and 1.4 times increase in the worst-case delay. The GeOI latch leakages are smaller than the SOI counterparts at 300°K (Vdd <; 0.8V) and 400°K (Vdd = 0.5~1.0V).