Title :
Parallel test pattern generation using Boolean satisfiability
Author :
Sivaramakrishnan, V. ; Seth, Sharad C. ; Agrawal, Prathima
Author_Institution :
Nebraska Univ., Lincoln, NE, USA
Abstract :
Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on Boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. This paper suggests parallel versions of Larrabee´s algorithm, suitable for implementation on shared-memory and message-passing multicomputers
Keywords :
Boolean functions; combinatorial circuits; logic testing; parallel algorithms; Boolean satisfiability; Larrabee´s algorithm; benchmark circuits; combinational circuits; message-passing multicomputers; parallel test pattern generation; shared-memory multicomputers; test generation algorithms; Benchmark testing; Circuit faults; Circuit testing; Circuit topology; Combinational circuits; Gold; Logic circuits; Logic testing; Sequential analysis; Test pattern generators;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185095
