Title :
Design of high-speed VLSI circuits for mainframe computers
Author :
Seinecke, Siegfried
Author_Institution :
Siemens Data & Inf. Syst., Munich, Germany
Abstract :
The next generation of mainframe computers will use fast BiCMOS ASICS having upto 100000 gate functions. Static CMOS RAMs with 3 ns access time will be embedded in bipolar ECL logic circuits with 50 ps gate delay. Standard cells will be intensively applied in order to obtain very fast macros with reduced power and space. Delay rules have to be designed in order to predict net delay and delay tolerances; line delay will dominate. The CAD system has to offer tools for optimum design of critical paths. TAB packages are the best choice
Keywords :
BIMOS integrated circuits; SRAM chips; VLSI; application specific integrated circuits; cellular arrays; circuit CAD; emitter-coupled logic; tape automated bonding; TAB packages; access time; bipolar ECL logic circuits; critical paths; delay tolerances; fast BiCMOS ASICS; fast macros; gate delay; gate functions; high-speed VLSI circuits; line delay; mainframe computers; net delay; optimum design; BiCMOS integrated circuits; CMOS logic circuits; Delay effects; Delay lines; Logic arrays; Logic circuits; Read-write memory; Resistors; Very large scale integration; Wiring;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185118
