Yield and layout issues in fault tolerant VLSI architectures

Author

Upadhyaya, Shambhu J. ; Chen, Yung-Yuan

Author_Institution

Dept. of Elect. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

fYear

1991

fDate

4-8 Jan 1991

Firstpage

255

Lastpage

260

Abstract

Yield and layout are two important but often ignored issues in the design of fault tolerant VLSI systems. The authors present a framework for the systematic analysis of yield and area-efficient layout of fault-tolerant architectures. A multiple level redundancy tree is considered as a target architecture to demonstrate their analysis technique

Keywords

VLSI; circuit layout CAD; circuit reliability; computer architecture; fault tolerant computing; microprocessor chips; multiprocessing systems; redundancy; trees (mathematics); VLSI architectures; area-efficient layout; fault-tolerant architectures; layout; multiple level redundancy tree; single-chip multiprocessors; yield; Assembly; Binary trees; Computer architecture; Fault tolerance; Fault tolerant systems; Multiprocessing systems; Redundancy; Switches; Very large scale integration; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Conference_Location

New Delhi

Print_ISBN

0-8186-2125-7

Type

conf

DOI

10.1109/ISVD.1991.185126

Filename

185126

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888907