Title :
Method for testable design and for built-in test
Abstract :
The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit
Keywords :
Built-in self-test; Circuit faults; Circuit testing; Design methodology; Electrical fault detection; Fault detection; Hardware; Logic design; Logic testing; Sequential analysis;
Conference_Titel :
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location :
New Delhi
Print_ISBN :
0-8186-2125-7
DOI :
10.1109/ISVD.1991.185136
