Energy-efficient instruction set architecture for CMOS microprocessors

Concern over power dissipation in CMOS microprocessors is increasing, not just for portable battery-based applications, but also for performance-driven designs, where power may soon displace silicon area as the principal design constraint. Traditional methods of power management, such as reduced operating voltage, exotic packaging, and low-power “sleep modes” can help mitigate the problem, but limits and drawbacks of these methods motivate an examination of processor architecture tradeoffs from a power perspective. This research was undertaken to validate the hypothesis that the instruction set architecture can have a significant effect on power-a smaller program encoding is more energy-efficient than a larger one. In this paper, we explore the relationship of code density and instruction set richness to the energy cost of fetching and delivering instructions to the execution resources. These effects are of particular interest to instruction-level parallel machines where speculative and multiple-path instruction fetching is necessary to exploit the high execution bandwidth