DocumentCode
2889515
Title
A 4Mb DRAM with double-buffer static-column architecture
Author
Parent, R. ; Morency, D. ; Kilmer, C. ; Tewarson, D. ; Newhart, R. ; Kosson, J. ; Clinton, Michael ; Bronson, T. ; Plouffe, D. ; Bus, M. ; Morrish, J. ; Thoma, E. ; Busch, R. ; Redman, T.
Author_Institution
IBM General Technology Division, Essex Junction, VT, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
14
Lastpage
15
Abstract
A 4Mb CMOS DRAM organized 1Mb×4, measuring 6.35mm × 12.3mm, and operating at a typical row access time of 65ns, will be described. The design utilizes a double buffer architecture to achieve a static column access time of 25ns. Half Vdd -folded bit-lines are used with a substrate plate trench storage structure resulting in a cell size of 10.5μm2.
Keywords
Capacitance; Circuit noise; Clocks; Decoding; Delay; Noise reduction; Random access memory; Solid state circuits; Variable structure systems; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157207
Filename
1157207
Link To Document