Pentium MPP for OLTP applications

Author

Natale, Mark ; Baker, Mark ; Collins, Roger ; Wilson, David ; Lucci, Stephen ; Gertner, Izidor

Author_Institution

Encore Comput. Corp., Fort Lauderdale, FL, USA

Volume

1

fYear

1995

fDate

3-6 Jan 1995

Firstpage

95

Abstract

The paper describes a multi-Pentium architecture with a hierarchical memory and an I/O bus subsystem. On a board-level, this architecture achieves a very high-level of integration, by accommodating 8 Pentium processors with up to 2 Gigabytes of RAM. This hierarchical architecture has been extended to support multiple boards in a single cabinet as well as multiple cabinets connected via reflective memory

Keywords

parallel architectures; random-access storage; shared memory systems; transaction processing; I/O bus subsystem; OLTP applications; Pentium MPP; Pentium processors; RAM; hierarchical architecture; hierarchical memory; massively parallel processing; multi-Pentium architecture; multiple boards; multiple cabinets; reflective memory; Application software; Bandwidth; Central Processing Unit; Cities and towns; Computer architecture; Computer science; Memory management; Operating systems; Processor scheduling; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

System Sciences, 1995. Proceedings of the Twenty-Eighth Hawaii International Conference on

Conference_Location

Wailea, HI

Print_ISBN

0-8186-6930-6

Type

conf

DOI

10.1109/HICSS.1995.375405

Filename

375405