FPGA Design of Box-Constrained MIMO Detector

In this paper, a box-constrained MIMO detector is considered that allows simple FPGA implementation and provides improvement in the detection performance compared to the MMSE detector. The box-constrained detector is implemented using dichotomous coordinate descent iterations. We investigate the design throughput against the BER performance and the design complexity in terms of the number of logic slices. The proposed design requires as few as 637, 658, and 667 slices for 4 times 4, 8 times 8, and 16 times 16 MIMO systems, respectively, which is significantly less than that required by known designs of the MMSE detector.