Chip-package thermal co-simulation technique for thermally aware chip design

This paper proposes an early stage, fast and accurate approach for a temperature aware, chip level circuit design. In essence, the strategy involves up front characterization of the package and the surroundings using rigorous thermal simulation techniques for on-demand available, automated and accurate thermal model for the silicon design team. The model takes as input, the chip power map and outputs steady state temperature map. This was accomplished by using a method of linear superposition for characterizing the detailed model of a chip along with its packaging and relevant surroundings. The proposed repository of compact models in library form obviates the need for advanced background in heat transfer or time consuming computations at the point of use which have traditionally been a bottleneck to early stage adoption of thermal management during chip design.