• DocumentCode
    2890494
  • Title

    RVC-based time-predictable faulty caches for safety-critical systems

  • Author

    Abella, Jaume ; Nones, Eduardo Qui ; Cazorla, Francisco J. ; Valero, Mateo ; Sazeides, Yanos

  • Author_Institution
    Barcelona Supercomput. Center, Barcelona, Spain
  • fYear
    2011
  • fDate
    13-15 July 2011
  • Firstpage
    25
  • Lastpage
    30
  • Abstract
    Technology and Vcc scaling lead to significant faulty bit rates in caches. Mechanisms based on disabling faulty parts show to be effective for average performance but are unacceptable in safety critical systems where worst-case execution time (WCET) estimations must be safe and tight. The Reliable Victim Cache (RVC) deals with this issue for a large fraction of the cache bits. However, replacement bits are not protected, thus keeping the probability of failure still high. This paper proposes two mechanisms to tolerate faulty bits in replacement bits and keep time-predictability by extending the RVC. Our solutions offer different tradeoffs between cost and complexity. In particular, the Extended RVC (ERVC) has low energy and area overheads while keeping complexity at a minimum. The Reliable Replacement Bits (RRB) solution has even lower overheads at the expense of some more wiring complexity.
  • Keywords
    cache storage; safety-critical software; software fault tolerance; ERVC; RRB; RVC; RVC-based time-predictable faulty caches; WCET; extended RVC; faulty bit rates; reliable replacement bits; reliable victim cache; safety-critical systems; worst-case execution time estimation; Arrays; Bit rate; Cache memory; Circuit faults; Random access memory; Reliability; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International
  • Conference_Location
    Athens
  • Print_ISBN
    978-1-4577-1053-7
  • Type

    conf

  • DOI
    10.1109/IOLTS.2011.5993806
  • Filename
    5993806