Calculating resettability and reset sequences

A synchronous sequential design is resettable if there is a finite sequence of primary input vectors (called a reset or synchronizing sequence) and a single state (called a reset state) such that application of the reset sequence to any initial state of the design drives the design into the reset state. New, efficient algorithms are presented to decide if a design is essentially and actually resettable, to find essential and actual reset sequences, to find the set of essential reset states and an actual reset state, and to check that an alleged essential or actual reset sequence essentially or actually resets a design. These algorithms are based on the results of a theory of design equivalence presented by C. Pixley (1990), and C. Pixley and G. Beihl (1991). The algorithms are implemented in the MCC CAD Sequential Equivalence Tool and future optimizations among well-established lines promise greater speed and applicability to much larger designs.<>