DocumentCode :
2891076
Title :
Soft error correction in embedded storage elements
Author :
Imhof, Michael E. ; Wunderlich, Hans-Joachim
Author_Institution :
Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Stuttgart, Germany
fYear :
2011
fDate :
13-15 July 2011
Firstpage :
169
Lastpage :
174
Abstract :
In this paper a soft error correction scheme for embedded storage elements in level sensitive designs is presented. It employs space redundancy to detect and locate Single Event Upsets (SEUs). It is able to detect SEUs in registers and employ architectural replay to perform correction with low additional hardware overhead. Together with the proposed bit flipping latch an online correction can be implemented on bit level with a minimal loss of clock cycles. A comparison with other detection and correction schemes shows a significantly lower hardware overhead.
Keywords :
clocks; error correction; flip-flops; bit flipping latch; clock cycles; embedded storage elements; level sensitive designs; single event upsets; soft error correction scheme; Clocks; Hardware; Latches; Logic gates; Redundancy; Registers; Transistors; Correction; Latch; Register; Single Event Effect;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International
Conference_Location :
Athens
Print_ISBN :
978-1-4577-1053-7
Type :
conf
DOI :
10.1109/IOLTS.2011.5993832
Filename :
5993832
Link To Document :
بازگشت