DocumentCode :
2891183
Title :
Wafer fabrication factory simulation language
Author :
Pollak, Steven
Author_Institution :
Gen. Electr. Co., Schenectady, NY, USA
fYear :
1989
fDate :
22-24 May 1989
Firstpage :
114
Lastpage :
116
Abstract :
In the current semiconductor processing environment, the challenge lies in maximizing throughput despite constant changes of technology and product mix. Factory simulation can help analyze these critical processing variables and improve profitably. Although there are many good off-the-shelf simulation development tools, none of them can easily be applied to the wafer fabrication facility with its circular job shop flow and hundreds of processing steps. The author addresses this problem from two angles. First, the advantages of using factory (discrete event) simulation in the wafer fabrication facility are discussed. Second, attention is given to how a wafer fabrication facility simulation language was developed to tackle the problem of designing simulations for the wafer fabrication environment
Keywords :
VLSI; digital simulation; electronic engineering computing; integrated circuit manufacture; semiconductor device manufacture; simulation languages; VLSI manufacture; circular job shop flow; factory simulation language; semiconductor processing environment; wafer fabrication facility; Analytical models; Costs; Discrete event simulation; Fabrication; Manufacturing industries; Neck; Production facilities; Profitability; Research and development; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing Science Symposium, 1989. ISMSS 1989., IEEE/SEMI International
Conference_Location :
Burlingame, CA
Type :
conf
DOI :
10.1109/ISMSS.1989.77257
Filename :
77257
Link To Document :
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