Discrete-Time Modeling of Clock Jitter in Continuous-Time ΔΣ Modulators

This paper proposes a simple, yet accurate, discrete-time modeling technique for simulating the performance degradation in continuous-time ΔΣ modulators due to clock jitter. The proposed technique is based on the impulse-invariant transform and is applicable to modulators that employ nonreturn-to-zero (NRZ) or delayed return-to-zero (RZ) rectangular feedback pulses. It is also independent of both the loop transfer function of the ΔΣ modulator and the power spectrum of the clock jitter. Furthermore, a versatile clock generator is modeled in SIMULINK for accurate behavioral simulation of digital-to-analog converters (DACs) with arbitrarily-jittered rectangular pulses. This clock generator is used to confirm the accuracy and performance advantages of the proposed modeling technique.