Title :
A supervised neural network layer of continuously adapting, analog floating-gate nodes
Author :
Dugger, Jeff ; Srinivasan, Venkatesh ; Hasler, Paul
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
We present an LMS node based upon an improved continuously adapting, analog floating-gate synapse that exhibits minimal weight decay. Our approach is based upon a recently developed synapse element based upon our tradition on single-transistor learning synapses with minimal weight decay. We show the transition from a single floating-gate synapse element to a single floating-gate node, demonstrated using results from simple LMS experiments. We present experimental data from ICs fabricated in 0.5 μm CMOS process.
Keywords :
CMOS analogue integrated circuits; adaptive signal processing; analogue processing circuits; learning (artificial intelligence); least mean squares methods; logic gates; neural chips; CMOS process; ICs fabrication; LMS node; analog floating-gate node; continuous adaptive node; minimal weight decay; single floating-gate synapse element; single-transistor learning synapse; supervised neural network layer; Adaptive signal processing; Analog integrated circuits; Bandwidth; Computational efficiency; Computer architecture; Digital signal processing; Digital signal processing chips; Least squares approximation; Neural networks; Signal processing algorithms;
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN :
0-7803-8104-1
DOI :
10.1109/ACSSC.2003.1292337