A 3-ps dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies

This work proposes a double-edge-checking phase frequency detector (dec-PFD), designed in 0.35-μm CMOS process with 3-V supply voltage. Consisting of four-states without feedback paths, the dec-PFD can avoid U_p and D_OWN signals from rising to high at the same time and thus solve current mismatch problem with 3-ps dead-zone in the phase detection. The maximum operating frequency of the PFD is 4.78 GHz. Simulated results are presented to demonstrate the capability of phase detection of the circuit.