A Set Associative Cache Architecture

Traditional set associative caches have fixed number of sets with fixed number of ways in each set. This paper proposes a new set associative architecture. The mapping of an address to a set is expanded to a subset of the number of sets by XOR´ing the address with 0, 1, 2, 4... (number of sets/2). The line is placed in any of the available ways in this mapping. If the cache is full, the cache is like a traditional set associative cache. The number of ways that a line can be placed in a partially filled cache is increased by this mapping. The algorithm is simulated on SPEC 2K benchmarks. An average decrease of 13% in average memory access time is observed. The average memory access time for 256.bzip2 shows degradation. The consumption of energy increases as a function of the cache size.