A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V

In this work, two cross-coupled PMOS (CC-PMOS) devices are placed between each local bit-line. Voltage differential that is created on local bit-lines during read and write operations are preserved by CC-PMOS structure. Simulated waveforms demonstrate a sample case where localBL discharges to OV before word-line boosting takes place causing functional failure. Addition of CC-PMOS devices fight bit-cell transistors and preserve the differential between local bit-lines. In layout, these devices are designed to fit into the bit-cell NWELL strip introducing less than 3% area overhead.