"Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC

Author

McNeill, John A. ; Goluguri, Sanjeev ; Nair, Abhilash

Author_Institution

Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA

fYear

2007

fDate

27-30 May 2007

Firstpage

1237

Lastpage

1240

Abstract

The "split ADC" architecture concept is applied to correction of errors due to nonlinearity of an open-loop residue amplifier in a pipeline ADC. Determination of calibration parameters and correction of errors takes place entirely in the background in the digital domain; no interaction with analog circuitry is required. An algorithm exhibiting convergence of calibration parameters in fewer than 100 000 conversions is presented.

Keywords

adaptive systems; amplifiers; analogue-digital conversion; calibration; error correction; mixed analogue-digital integrated circuits; 14 bit; adaptive systems; analog-digital conversion; calibration parameters; digital background calibration; error correction; mixed analog-digital integrated circuits; nonlinearity errors; open-loop residue amplifier; pipeline ADC; split-ADC; Adaptive systems; Calibration; Circuits; Computer architecture; Computer errors; Convergence; Electronic mail; Error correction; Gain; Pipelines; Analog-digital conversion; adaptive systems; calibration; digital background calibration; mixed analog-digital integrated circuits; pipeline ADC; self-calibrating;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378334

Filename

4252869