A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs

This paper presents a gradient-based algorithm for the sampling clock skew calibration of SHA-less pipeline analog-to-digital converters (ADCs). Based on the skew information collected from the output residues of the first pipeline stage, the clock of the sub-ADC is adaptively adjusted to synchronize with that of the sample-and-hold (S/H) in the first pipeline stage. This clock skew calibration technique essentially improves the viability of the SHA-less architecture for pipeline ADCs at high input frequencies. It follows that the power consumption of pipeline ADCs can be substantially reduced by eliminating the dedicated, power-hungry front-end sample-and-hold amplifier (SHA) and remedying the resulting sampling clock skew problem by adaptive calibration.