Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell

Author

Feki, Afef ; Allard, Bruno ; Turgis, D. ; Lafont, J. ; Ciampolini, L.

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

470

Lastpage

474

Abstract

The tendency for low energy consumption in systems-on-chip results in a need for memories operating in the near- and sub-threshold regions. This paper gives a comparative study of Static Random Access Memory (SRAM) bitcells working under Ultra-Low Voltage in 32nm CMOS. A new 10T SRAM bitcell is then proposed and features low leakage current. It is capable of operation under ULV (~300mV) and allows bit-interleaving technique that is critical to cope with multiple bit soft-errors for reducing dynamic and static power consumption compared to state-of-the-art bitcells.

Keywords

CMOS integrated circuits; SRAM chips; low-power electronics; system-on-chip; CMOS; SRAM; bit-interleaving technique; dynamic power consumption; low energy consumption; multiple bit soft-errors; static power consumption; static random access memory; systems-on-chip; ultra-low voltage; voltage 300 mV; wavelength 32 nm; CMOS integrated circuits; Computer architecture; Discharges (electric); Leakage current; Power demand; Random access memory; Transistors; Bitcell; Leakage; SRAM; Sub threshold Design; half selected bitcells;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2012 International

Conference_Location

Jeju Island

Print_ISBN

978-1-4673-2989-7

Electronic_ISBN

978-1-4673-2988-0

Type

conf

DOI

10.1109/ISOCC.2012.6406898

Filename

6406898